At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, ...

A new technical paper titled “3D integration of pixel readout chips using Through-Silicon-Vias” was published by researchers at CERN, IZM Fraunhofer and University of Geneva. “Particle tracking and ...

In industry, we see more and more examples of systems being built through heterogeneous integration leveraging 2.5D or 3D connectivity. In this interview, Eric Beyne, Senior Fellow, VP R&D and Program ...

The steady march toward 3D ICs, namely mixed-signal or multi-technology systems-on-chip (SoC) or systems-in-package (SiP), is becoming a brisk jog. With a mix of military and government funding, and ...

CEA-Leti, the coordinator of the FAMES Pilot line, has achieved a major milestone for next-generation chip stacking: fully functional 2.5 V SOI CMOS devices fabricated at 400 °C. The devices match ...